1. Technical Field of the Invention
The present invention generally relates to methods for forming ultra-shallow junctions in semiconductor wafers by ion implantation of dopants and, more particularly, to methods for controlling junction depth and narrowing dopant concentration profile by minimizing dopant channeling during implantation and retarding dopant diffusion during subsequent thermal annealing.
2. Description of Related Art
The semiconductor technology central to the modem integrated circuit has been developing for over a century. The special properties of the semiconductor selenium were first observed and recognized in the late nineteenth century. The first transistor design was proposed during the 1930s. However, a functional point contact transistor was not constructed until the late 1940s. For the next ten years, the field of electronics was dominated by the use of discrete circuit components—e.g., transistors, resistors and capacitors—in circuit design. The integrated circuit, which employs a plurality of circuit components in a single monolithic semiconductor substrate rather than using discrete components, was first developed in the late 1950s by inventor Jack Kilby at Texas Instruments, Inc.
Since the late 1950s, integrated circuit technology has evolved rapidly and has revolutionized virtually every industry and capacity in which electronics are used. The proliferation of electronics in general, and integrated circuits in particular, has resulted in large part from the ability to increase circuit functionality while simultaneously reducing device cost and size. A principal catalyst for these improvements has been a number of advances in semiconductor processing technologies, the various techniques used to construct integrated circuits on the semiconductor substrate. Improved materials, equipment and processes have allowed increasingly complex circuits possessing improved speed, requiring less power, and occupying less space.
Integrated circuits are typically constructed at the surface of crystalline silicon wafers, although other semiconductor materials such as gallium arsenide and germanium are also used. Individual circuit components are formed in and on the wafer surface. The electrical interconnectivity between circuit elements is then established above the semiconductor substrate using alternating layers of appropriately patterned conductors and insulators. The circuit components and their interconnections are formed using a series of well-known processing steps including photolithography, thin film deposition, selective etching, ion implantation and thermal processing.
For the last two decades, metal-oxide semiconductor (MOS) technology has occupied a central role in integrated circuit design. The heart of the MOS integrated circuit is the metal-oxide semiconductor field-effect transistor (MOSFET), which serves as a high-speed switch. In the MOSFET, the conductivity through a thin channel located between a source electrode and a drain electrode is controlled by a voltage applied to a gate electrode located in proximity to the channel. Ideally, a MOSFET exhibits high drive current and low internal impedance in the “on” state and exhibits high internal impedance and low current leakage in the “off” state. MOSFETs offer remarkable noise immunity, operability over wide voltage ranges, and a number of other desirable properties that make them ideal for logic circuitry.
MOSFETs can be categorized as either n-type or p-type, depending on the manner in which the source electrode, drain electrode and channel are doped. In an n-type MOSFET, the source and drain of the transistor are doped with an n-type dopant that is electron rich relative to silicon—e.g., arsenic and phosphorous—while the channel is doped with a p-type dopant that is electron deficient relative to silicon—e.g., boron and indium. The insertion of an n-type dopant in the semiconductor lattice results in an additional electron in the conduction band of the semiconductor. Because conduction-band electrons are majority charge carriers in an n-type MOSFET, current conduction is primarily via conduction-band electrons. Consequently, conduction through the p-doped channel of a n-type MOSFET occurs only when the potential applied to the gate electrode results in a substantial concentration of conduction-band electrons in the channel.
Conversely, in an p-type MOSFET, the source and drain electrodes are doped with a p-type dopant and the channel is doped with an n-type dopant. The insertion of a p-type dopant in the semiconductor lattice results in a valence-band “hole”—i.e., a positively-charged electron deficiency in the valence band of the semiconductor—that can move under the application of an external electric field. Because conduction-band electrons are minority charge carriers and valence-band holes are majority charge carriers in a p-type MOSFET, current conduction is primarily via valence-band holes. Consequently, conduction through the n-doped channel of a p-type MOSFET occurs only when the potential applied to the gate electrode results in a substantial concentration of valence-band holes in the channel.
Current integrated circuit designs using ultra large scale integration (ULSI) frequently utilize as many as several hundred million circuit elements. The increasing packing density in these circuits generates numerous challenges to the semiconductor manufacturing process: the dimensions of each circuit element must shrink in each product generation without degrading the characteristics and the operations of the integrated circuit. The commercial popularity of the MOSFET in circuit design is due partly to its scalability. Scaling of these devices is advantageous for several reasons. First, it increases the device packing density, thereby reducing the size of the integrated circuit. Second, scaling to smaller dimensions improves the frequency response of the transistor, whose signal propagation time is proportional to the inverse of the length of the channel. Third, decreasing the channel length and gate oxide thickness increases transistor transconductance, which increases the current drive of the transistor.
As MOSFET dimensions continue to shrink, further scaling becomes increasingly difficult, in part because of so-called “short-channel effects.” In devices with long channel lengths, the gate voltage is principally responsible for depleting majority charge carriers and attracting minority charge carriers in the channel, a process known as inversion. In very short channel devices, in contrast, the electric fields generated by the source and drain can contribute to the inversion in the channel. These short-channel effects decrease the threshold gate voltage (Vt) required for inversion and for conduction through the channel. In such cases, Vt is not constant and instead decreases as the drain and source fields increase, a phenomenon known as Vt rolloff. This effect is particularly prominent when high drain voltages are employed, leading to drain-induced barrier lowering (DIBL). DIBL is the effect a drain voltage has on the output conductance and measured Vt. It is observed as a variation of the measured threshold voltage with reduced gate length. In the case of very short channels and high drain voltages, the inversion region can extend across the channel without regard to the gate voltage. In such cases, referred to as “punchthrough,” the transistor is locked in the “on” state. Thus, as MOSFET dimensions shrink, “short channel effects” such as junction punchthrough, the leakage, and the contact resistance, degrade transistor performance and reliability.
The control of “short-channel effects” in MOSFETs is one of the biggest challenges in scaling to sub-0.1 micron dimensions. Because short-channel effects occur in MOSFETs when only the gate length is reduced without properly scaling the other MOSFET dimensions, these undesirable effects can be mitigated by also scaling the source and drain electrodes. This is accomplished by employing ultra-shallow extensions to the source and drain region that are partially disposed underneath the gate electrode. Simply put, as the lateral dimensions of the MOSFET channel are scaled down to 100 nm and below, the source/drain (S/D) extension junction depth must be proportionately reduced to below 30 nm in order to suppress short-channel effects. Furthermore, the sheet resistance of the S/D extension regions must be decreased so that they do not add significant resistance to the channel resistance. This means that ever higher active dopant concentrations must be achieved in the ultra-shallow S/D extension regions.
The Semiconductor Industry Association (SIA) has developed the National Technology Roadmap for Semiconductors (NTRS), a roadmap for the next several generations of integrated circuit devices. According to the 1997 SIA NTRS, as device geometries shrink from 0.25 micron (μm) to 0.1 μm, the junction depth will need to decrease from 750 nanometers (nm) to 30 nm. At the same time, the dopant concentration in the junction will need to increase by approximately a factor of five to maintain acceptable sheet resistance. Consequently, much research has been directed towards establishing ultra-shallow S/D extensions, also known as ultra-shallow junctions, with high dopant concentrations.
Unfortunately, a variety of factors render the formation of ultra-shallow junctions in semiconductor substrates difficult. In particular, dopant channeling during ion implantation processes and dopant diffusion during thermal activation processes tend to broaden the junctions. Despite these difficulties associated with forming ultra-shallow junctions in semiconductor substrates, such junctions are a necessary component of future MOSFET designs. What is needed is a method for forming ultra-shallow junctions in MOSFETs that overcomes the effects of dopant channeling during the ion implantation and dopant diffusion during thermal activation and thereby offers resistance to short-channel effects in next generation MOSFETs and other integrated circuit components.